A prior art semiconductor-on-insulator construction is described with reference to FIG. 1. Specifically, FIG. 1 illustrates a fragment 10 of a semiconductor-on-insulator construction. The construction includes a substrate 12 having an insulative material 14 formed thereover, and further comprises a semiconductor-containing material 16 formed over insulative material 14.
Substrate 12 can comprise, for example, silicon and/or germanium. If the substrate comprises silicon, the silicon can be in the form of, for example, polycrystalline silicon and/or monocrystalline silicon. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Insulative material 14 can comprise, consist essentially of, or consist of silicon dioxide and/or nitrided oxides.
Semiconductor-containing material 16 can comprise, consist essentially of, or consist of monocrystalline silicon or other semiconductor materials, such as, for example, SiGe heterostructures. In particular applications, semiconductor-containing material 16 will consist essentially of, or consist of, monocrystalline silicon doped with either an n-type dopant or a p-type dopant, with an exemplary p-type dopant being boron.
A transistor device 18 is shown associated with semiconductor-containing material 16. Transistor device 18 includes a transistor gate 20 separated from semiconductor-containing material 16 by a dielectric material 22, and includes source/drain regions 26 and 28. Dielectric material 22 can comprise, for example, silicon dioxide, and can be referred to as a gate oxide. Gate 20 can comprise various conductive materials, including, for example, metals, metal alloys, silicides, and/or conductively-doped silicon. In particular applications, gate 20 will comprise a stack which includes, in ascending order from dielectric material 22, a layer of conductively-doped silicon, a layer of silicide, and a layer of metal.
Gate 20 defines a channel region 24 within semiconductor-containing material 16, and corresponding to a portion of the semiconductor-containing material 16 proximate the gate 20. In the shown construction, channel region 24 corresponds to the portion of semiconductor-containing material 16 immediately under gate 20, and separated from gate 20 by dielectric material 22.
Sidewall spacers 30 are formed along sidewall edges of gate 20. Sidewall spacers can comprise, for example, silicon nitride and/or silicon dioxide.
Source/drain regions 26 and 28 are formed within semiconductor-containing material 16, and separated from one another by channel region 24. Source/drain regions 26 and 28 can comprise, for example, n-type doped diffusion regions within semiconductor-containing material 16 and/or p-type doped diffusion regions within semiconductor-containing material 16. In the shown construction, the source/drain regions comprise a lightly-doped portion 32 beneath spacers 30, and a heavily-doped portion 34 laterally outward of lightly-doped portion 32 relative to channel region 24.
A continuing goal in semiconductor device fabrication is to reduce an amount of semiconductor real estate consumed by transistor devices. Several problems occur, however. For instance, problems can occur as the length of channel region 24 between source/drain regions 26 and 28 is decreased. Such problems are commonly referred to as short-channel effects. A particular effect which is found to become problematic is drain-induced barrier lowering (DIBL), which is due to charge sharing between the source and drain of a transistor device. DIBL results from lowering of a potential barrier at the source region due to high potential near the drain for short length devices.
It would be desirable to develop semiconductor constructions which alleviate, and preferably prevent, short-channel effects, as well as to develop methods of forming such constructions.